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1 e99946a9y-te sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. absolute maximum ratings (ta=25 c unless stated) ? supply voltage v cc 12 v ? storage temperature tstg C65 to +150 c ? allowable power dissipation p d 900 mw operating conditions ? supply voltage v cc 9+/C0.5 v ? typical supply current 75 ma ? operating temperature topr C20 to +75 c description the CXA2149Q is a video and audio switch ic featuring i 2 c bus compatibility for tvs. the ic has input pins that are compatible with the scart protocols. it offers other features such as an electronic mute function with switching noise reduction (zero cross detection), electronic volume control, automatic sync pulse detection, and group delay control. features ? 3 cvbs inputs. ? 2 cvbs outputs. ? group delay control on tv and cvin1. ? sync id on tv and cvin1. ? 3 y/c inputs. ? 2 y/c outputs. ? 6 l/r/2 inputs. ? 3 l/r/2 outputs. ? mode inputs compatible with the scart protocol. ? 3 y/c mixer circuits. ? audio muting via software control. ? external muting input. ? audio switching noise elimination circuit. ? volume adjustment via software control on l/r channel 3. ? wide band video amplifiers (20 mhz, C3 db). ? wide audio dynamic range (3 vrms typ) ? serial control via i 2 c bus. ? separate control of video and audio switches. ? high impedance maintained by i 2 c lines (sda, scl) even when power is off. ? configurable dual slave address 90/92. ? i 2 c bus 5 and 3.3 v compatible. applications tvs structure bipolar silicon monolithic ic i 2 c-bus-compatible audio/video switch 64 pin qfp (plastic) CXA2149Q
2 CXA2149Q block diagram r e x t t v o u t r g d 4 r g d 3 l o 0 r g d 2 r g d 1 l o 1 c v o u t 1 t r a p 1 y o u t 1 c o u t 1 s c l s d a a d r m u t e m o d e 1 m o d e 2 c 2 c 3 c o u t 2 t r a p 2 y o u t 2 d v c c c v o u t 2 d g n d l o u t 2 r o u t 2 l o u t 1 r o u t 1 r v 1 r v 2 r v 3 r v 4 r v 5 r t v a g n d l v 1 l v 2 l v 3 l v 4 l v 5 l t v r o u t 3 l o u t 3 a b i a s a v c c m o d e 3 c 1 y 3 t r a p 3 v b i a s y 2 v g n d 1 , 2 y 1 v v c c 1 , 2 c v i n 2 t c 2 c v i n 1 t c 1 t v s y n c d e t e c t g r o u p d e l a y s i c 6 d b 6 d b 0 d b 0 d b 6 d b 0 d b 0 d b 6 d b 6 d b 6 d b 6 d b 6 d b 6 d b i c l o g i c b i a s b i a s 6 d b 6 d b 0 t o 6 3 d b 0 t o 6 3 d b 3 8 3 9 4 0 4 1 2 1 2 3 2 4 2 9 1 1 1 0 1 3 4 5 4 7 4 6 4 3 5 9 1 2 5 5 5 7 2 2 3 1 6 1 6 3 1 3 4 6 7 6 0 6 2 6 4 5 4 5 3 5 6 5 8 4 9 5 1 5 2 1 4 1 5 1 6 1 7 1 8 1 9 4 2 4 4 2 0 5 8 2 5 2 6 2 7 2 8 2 9 3 0 3 3 3 4 3 5 3 6 3 7 3 2 2 i c 2 2 , 4 8 ,
3 CXA2149Q pin configuration 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 r e x t t v o u t r g d 4 r g d 3 l o 0 r g d 2 r g d 1 l o 1 c v o u t 1 t r a p 1 y o u t 1 v v c c 2 c o u t 1 s c l s d a a d r m u t e m o d e 1 m o d e 2 c 2 n c c 3 v g n d 2 c o u t 2 t r a p 2 y o u t 2 d v c c c v o u t 2 d g n d l o u t 2 r o u t 2 l o u t 1 r o u t 1 r v 1 r v 2 r v 3 r v 4 r v 5 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 r t v a g n d l v 1 l v 2 l v 3 l v 4 l v 5 l t v r o u t 3 l o u t 3 a b i a s a v c c m o d e 3 c 1 t r a p 3 y 3 v b i a s y 2 v g n d 1 y 1 v v c c 1 c v i n 2 t c 2 c v i n 1 t c 1 t v c x a 2 1 4 9 q
4 CXA2149Q pin description 64 62 60 58 56 54 52 51 49 25 30 29 28 27 26 32 37 36 35 34 33 9 43 11 45 13 47 2 tv cvin1 cvin2 y1 y2 y3 c1 c2 c3 ltv lv1 lv2 lv3 lv4 lv5 rtv rv1 rv2 rv3 rv4 rv5 cvout1 cvout2 yout1 yout2 cout1 cout2 tvout 3.9 4.5 4.5 3.8 3.5 4.5 3.8 pin symbol pin equivalent circuit description no voltage (v) 5 4 5 6 5 8 6 0 6 2 6 4 v c c 0 . 5 1 4 7 v c c 1 0 0 1 4 7 2 0 k 4 9 5 1 5 2 5 . 2 v v c c 3 3 k 3 3 k 4 . 5 v 2 5 2 6 2 7 2 8 2 9 3 0 3 2 3 3 3 4 3 5 3 6 3 7 v c c 1 . 8 m 2 9 1 1 1 3 4 3 4 5 4 7 video signal inputs. luminance signal inputs. chrominance signal inputs. audio signal inputs. composite video signal outputs. luminance signal outputs. chrominance signal outputs. tv signal group delayed output.
5 CXA2149Q 7 3 6 4 1 44 59 12 21 42 57 48 31 rgd1 rgd4 rgd2 rgd3 rext dvcc vvcc1 vvcc2 avcc dgnd vgnd1 vgnd2 agnd 4.5 4.5 1.7 9 0 pin symbol pin equivalent circuit description no voltage (v) v c c 0 . 5 m 3 7 v c c 1 . 7 k 4 6 v c c 3 . 8 v 1 group delay output to external filter. group delay inputs from external filter. pin connection for 39 k group delay setting resistor. pin voltage is group delay control dependent. digital supply. video supply. video supply. audio supply. digital ground. video ground. video ground. audio ground.
6 CXA2149Q 39 41 23 38 40 24 22 55 14 15 16 17 lout1 lout2 lout3 rout1 rout2 rout3 abias vbias scl sda adr mute 4.5 4.5 4.5 pin symbol pin equivalent circuit description no voltage (v) v c c 4 . 5 v 2 2 2 0 k 2 0 k v c c 4 . 5 v 5 5 1 4 1 5 4 k audio signal outputs. internal reference bias for audio circuits. a capacitor is connected from this pin to gnd. internal reference bias for video circuits. a capacitor is connected from this pin to gnd. i 2 c bus clock line. i 2 c bus data line. slave address control. audio signal output mute. v c c 7 2 k 2 8 k 1 6 1 7 v c c 2 3 2 4 3 8 3 9 4 0 4 1 5 6 2 0 k
7 CXA2149Q 5 8 18 19 20 63 61 10 46 53 lo0 lo1 mode1 mode2 mode3 tc1 tc2 trap1 trap2 trap3 5 3.5 pin symbol pin equivalent circuit description no voltage (v) v c c 5 8 i c c o n t r o l 2 2 5 k 2 5 k 1 9 1 8 2 0 v c c 1 4 7 6 1 6 3 v c c 2 0 0 2 0 0 4 6 1 0 5 3 open collector logic outputs. function scart inputs from scart connectors. video detect time constant capacitor connection pins. connects trap circuit for subcarrier. note. pin voltages indicated the approximate dc voltage levels with no signals inputs.
8 CXA2149Q electrical characteristics (ta=25 c, v cc =9 v unless stated.) item supply voltage supply current symbol v cc i cc conditions min. typ. max. unit 8.5 9.0 9.5 v 40 75 100 ma i 2 c (operation of the i 2 c using either a 3.3 or 5 v supply on the external controller is possible) item high level input voltage low level input voltage low level output voltage max. clock frequency min. waiting time for data change min. waiting time for data transfer start low level clock pulse width high level clock pulse width min. waiting time for start preparation min. data hold time min data preparation time rise time fall time min. waiting time for stop preparation symbol v ih v il v ol f scl t buf t hd sta t l t h t su sta t hd dat t su dat t r t f t su sto conditions sda 3 ma sink min. typ. max. unit 2.3 5 v 0 1.5 v 0 0.4 v 0 100 khz 4.5 s 4 s 4.7 s 4 s 4.7 s 5 s 250 ns 1 s 300 ns 4.7 50 s
9 CXA2149Q audio system item gain channel 1/channel 2 channel 3 (max.) channel 3 (min.) C3 db bandwidth total harmonic distortion input dynamic range crosstalk ripple rejection ratio output dc offset input impedance output impedance phase difference s/n ratio mute volume control fine coarse symbol fgv a1 vgv af vgv a0 fbw a thd vdr a vct a rr a voff zin zout vpd a s/n a amute fevc cevc conditions f=1 khz, 1 vp-p i/p. 1 vp-p i/p, 1 khz serving as 0 db ref. f=1 khz, 0.5 vp-p i/p with a 400 hz to 80 khz passband. f=100 khz, distortion at o/p less than 0.3 % f=1 khz, 1 vp-p i/p, measure other outputs. f=100 hz, 0.3 vp-p signal applied to avcc offset voltage between i/p and o/p. f=1 khz, 1 vrms input. compare left and right channels. f=1 khz, 1 vp-p input with a 20 hz to 20 khz passband. see note 1. f=1 khz, 1 vp-p input. f=1 khz, 0.5 vp-p input. min. typ. max. unit C0.5 0 0.5 db C0.5 0 0.5 db C68 C63 C58 db 1 mhz 0.01 0.05 % 2.8 3.0 vrms C90 C76 db C55 db C30 0 30 mv 66 k 20 0.1 deg 85 90 db C90 C70 db 0.6 1 1.4 db 7.6 8 8.4 db audio system notes 1. channel 3 should be set at maximum volume.
10 CXA2149Q video system item cvout1/2 gain y/cout1/2 gain C3 db bandwidth C3 db bandwidth y/c mixer input level, tv and cvin1 input dynamic range, cvin2 and y inputs. crosstalk s/n ratio differential gain differential phase group delay sync identification detected when sync amplitude sync duty cycle not detected when sync amplitude sync duty cycle symbol gv cv gv yc f bwv1 f bwv2 v riv v drv v c t v s/n v dg dp gd sync 1 conditions f=200 khz, 0.3 vp-p i/p. f=200 khz, 0.3 vp-p i/p. 0.3 vp-p i/p. see note 1. 0.3 vp-p i/p. see note 1. f=200 khz, distortion at o/p less than 1 %, gd=off f=200 khz, distortion at o/p less than 1.0 %. f=4.43 mhz, 0.7 vp-p i/p, measure other outputs. ratio of 0.7 vp-p white level to black line noise. 5 khz to 5 mhz passband. see note 2. 1.4 vp-p 5 step staircase, modulated with 150 mvp-p 4.43 mhz. as above. f=200 khz, 0.7 vp-p. see figure 1 and note 3. see note 4. 64 s period. 64 s period. min. typ. max. unit 5.5 6 6.5 db C0.5 0 0.5 db 15 20 mhz 10 15 mhz 1.4 vp-p 1.7 vp-p C55 db 72 db C1.5 0 1.5 % C1.5 0 1.5 deg 200 250 350 ns 100 mv 91 % 30 mv 84 % f i g u r e 1 g r o u p d e l a y c h a r a c t e r i s t i c f r e q u e n c y ( h z ) 4 . 5 4 3 . 5 3 2 . 5 2 1 . 5 1 0 1 2 3 4 5 6 g r o u p d e l a y ( s e c o n d s ) 1 0 7 1 0 6
11 CXA2149Q video system notes 1. 200 khz is taken to be 0 db for the purpose of this measurement. where applicable, the group delay function will be turned off to make this measurement. 2. weighted using ccir567. 3. this group delay characteristic, figure 1, is for the b, g specifications. it does not take into account the input and output delays inherent within the av switch. 4. the sync detection circuits operate on the video sources that have been switched into the tv and cvin1 channels, respectively. the internal sync discriminator circuit functions in the following way. the sync tip of the incoming video input is clamped to a fixed level and the signal is then compared in magnitude with an internal threshold voltage. if the signal is smaller than the threshold level the ic determines that the sync does not exist. conversely, if the signal is found to be greater than the threshold then the duty cycle of signal is passed to the duty discrimination circuit. the discriminator circuit will identify whether the duty cycle of the signal is above 91 % at which point sync is detected, or below 84 % when sync is not detected. to prevent occasional video disturbances such as if noise from the tuner causing malfunctioning of the sync detector, a time constant of approximately 14 line periods is applied during which the status of the sync detection is maintained.
12 CXA2149Q video system test configuration (gain, dynamic range, bandwidth, signal to noise, crosstalk, differential gain, differential phase, sync id, group delay) signals applied to inputs on pins 64, 62, 60, 58, 56, 54, 52, 51, 49 output signal measured form pins 9, 11, 13, 43, 45, 47 notes: 1) all +9 v supplies de-coupled close to supply pins 21, 44, 59 with 10 nf ceramic capacitor. 2) refer to application schematic for external pin configuration of sync detect circuits. 3) input signal assumes 75 ohm video driver. all video outputs are loaded with an emitter follower during tests. r e x t t v o u t r g d 4 r g d 3 l o 0 r g d 2 r g d 1 l o 1 c v o u t 1 t r a p 1 y o u t 1 v v c c 2 c o u t 1 s c l s d a a d r m u t e m o d e 1 m o d e 2 c 2 n c c 3 v g n d 2 c o u t 2 t r a p 2 y o u t 2 d v c c c v o u t 2 d g n d l o u t 2 r o u t 2 l o u t 1 r o u t 1 r v 1 r v 2 r v 3 r v 4 r v 5 r t v a g n d l v 1 l v 2 l v 3 l v 4 l v 5 l t v r o u t 3 l o u t 3 a b i a s a v c c m o d e 3 c 1 t r a p 3 y 3 v b i a s y 2 v g n d 1 y 1 v v c c 1 c v i n 2 t c 2 c v i n 1 t c 1 t v c x a 2 1 4 9 q 1 0 0 n f 1 0 0 n f 1 0 0 n f 7 5 7 5 7 5 + 9 v + 1 2 v 1 k b c 5 4 7 b + 1 2 v 1 k b c 5 4 7 b + 1 2 v + 1 2 v 1 k b c 5 4 7 b b c 5 4 7 b 1 k 1 0 0 n f 1 0 0 n f 7 5 1 0 0 n f 7 5 1 0 0 n f 7 5 1 f 7 5 1 0 0 n f 7 5 + 9 v + 9 v 1 f 7 5 i n p u t s i g n a l 1 0 f 1 0 0 n f v m e a s u r e m e n t p o i n t + 1 2 v b c 5 4 7 b 1 k + 1 2 v b c 5 4 7 b 1 k + 1 2 v b c 5 4 7 b 1 k 2 0 0 2 0 0 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 1 0 f i c 2 3 9 k 3 . 3 k 3 . 3 k 3 . 3 k 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 video test configuration
13 CXA2149Q audio system test configuration (gain, dynamic range, signal to noise, crosstalk, distortion, volume control, zcd and mute) signals applied to inputs on pins 25, 26, 27, 28, 29, 30, 32, 33, 34, 35, 36, 37 output signal measured form pins 23, 24, 39, 40, 41 notes: 1) all +9 v supplies de-coupled close to supply pins 21, 44, 59 with 10 nf ceramic capacitor. 2) when muting audio using hardware mute, sw1 is closed. r e x t t v o u t r g d 4 r g d 3 l o 0 r g d 2 r g d 1 l o 1 c v o u t 1 t r a p 1 y o u t 1 v v c c 2 c o u t 1 s c l s d a a d r m u t e m o d e 1 m o d e 2 c 2 n c c 3 v g n d 2 c o u t 2 t r a p 2 y o u t 2 d v c c c v o u t 2 d g n d l o u t 2 r o u t 2 l o u t 1 r o u t 1 r v 1 r v 2 r v 3 r v 4 r v 5 r t v a g n d l v 1 l v 2 l v 3 l v 4 l v 5 l t v r o u t 3 l o u t 3 a b i a s a v c c m o d e 3 c 1 t r a p 3 y 3 v b i a s y 2 v g n d 1 y 1 v v c c 1 c v i n 2 t c 2 c v i n 1 t c 1 t v c x a 2 1 4 9 q 1 f 1 k + 9 v 1 0 0 n f + 9 v + 9 v + 5 v 1 0 f 1 0 0 n f 2 0 0 2 0 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 1 0 f 1 f 1 k 1 f 1 k 1 f 1 k 1 f 1 k 1 0 f 1 0 f 1 0 f 1 0 f 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 v 1 0 k m e a s u r e m e n t p o i n t s w 1 h w m u t e 1 0 f 1 f 1 0 f 1 k 1 f 1 k 1 f 1 k 1 f 1 k 1 f 1 k 1 f 1 k 1 f 1 k i n p u t s i g n a l 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 i c 2 audio test configuration
14 CXA2149Q dc tests (audio and video system) notes: 1) all +9 v supplies de-coupled close to supply pins 21, 44, 59 with 10 nf ceramic capacitor. 2) all video outputs are loaded with an emitter follower during test. r e x t t v o u t r g d 4 r g d 3 l o 0 r g d 2 r g d 1 l o 1 c v o u t 1 t r a p 1 y o u t 1 v v c c 2 c o u t 1 s c l s d a a d r m u t e m o d e 1 m o d e 2 c 2 n c c 3 v g n d 2 c o u t 2 t r a p 2 y o u t 2 d v c c c v o u t 2 d g n d l o u t 2 r o u t 2 l o u t 1 r o u t 1 r v 1 r v 2 r v 3 r v 4 r v 5 r t v a g n d l v 1 l v 2 l v 3 l v 4 l v 5 l t v r o u t 3 l o u t 3 a b i a s a v c c m o d e 3 c 1 t r a p 3 y 3 v b i a s y 2 v g n d 1 y 1 v v c c 1 c v i n 2 t c 2 c v i n 1 t c 1 t v c x a 2 1 4 9 q + 9 v 1 0 0 n f + 9 v + 9 v 1 0 f 1 0 0 n f 2 0 0 2 0 0 1 0 f v v i d e o o u t p u t s i g n a l m e a s u r e m e n t a u d i o i n p u t s i g n a l m e a s u r e m e n t i c 2 v v i d e o i n p u t s i g n a l m e a s u r e m e n t v a u d i o o u t p u t s i g n a l m e a s u r e m e n t v 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 dc test configuration
15 CXA2149Q i 2 c bus register assignment status register slave 1 0 0 1 0 0 adr r/w address data1 sync1 sync2 mode por status status status slave 1 0 0 1 0 0 adr r/w address data1 cvout1 cvout2 data2 lo0 lo1 ycout1 ycout2 control control data3 zcd aout3 aout1 aout2 switch mute data4 group aout3 delay data5 aout3 volume control aout3 volume control aout3l/r coarse fine switch data6 gd1 gd2 sync1 sync2 * * * * switch switch switch switch control registers note. 1. the names cvout1, ycout1, aout1 etc., refer to the particular output or outputs that the register controls. 2. * register undefined. status register descriptions sync detection circuits data1 bit 6 (sync1) and bit 7 (sync2) indicates whether a video signal is present or not. sync1 takes its input from tv and yout1. sync2 takes its input from cvin1 and yout2. sync1 or sync2 bit meaning 0 no sync 1 sync present
16 CXA2149Q mode status data1 bits 1 to 5 the mode inputs from the scart ports are driven at three different voltage levels to indicate the mode format of the port. these inputs are detected and then encoded to the status register in the following manner. input pin voltage meaning 0 to 2 v internal tv 4.5 to 7 v external 16:9 9.5 to 12 v external 4:3 mode status bits meaning meaning meaning for mode1 for mode2 for mode3 00000 internal tv internal tv internal tv 00001 external 16:9 internal tv internal tv 00010 external 4:3 internal tv internal tv 00011 internal tv external 16:9 internal tv 00100 external 16:9 external 16:9 internal tv 00101 external 4:3 external 16:9 internal tv 00110 internal tv external 4:3 internal tv 00111 external 16:9 external 4:3 internal tv 01000 external 4:3 external 4:3 internal tv 01001 internal tv internal tv external 16:9 01010 external 16:9 internal tv external 16:9 01011 external 4:3 internal tv external 16:9 01100 internal tv external 16:9 external 16:9 01101 external 16:9 external 16:9 external 16:9 01110 external 4:3 external 16:9 external 16:9 01111 internal tv external 4:3 external 16:9 10000 external 16:9 external 4:3 external 16:9 10001 external 4:3 external 4:3 external 16:9 10010 internal tv internal tv external 4:3 10011 external 16:9 internal tv external 4:3 10100 external 4:3 internal tv external 4:3 10101 internal tv external 16:9 external 4:3 10110 external 16:9 external 16:9 external 4:3 10111 external 4:3 external 16:9 external 4:3 11000 internal tv external 4:3 external 4:3 11001 external 16:9 external 4:3 external 4:3 11010 external 4:3 external 4:3 external 4:3 11011 to 11111 not used not used not used
17 CXA2149Q power on reset data1 bit 0 after power on this bit will be set to 1 when dvcc, pin 44, passes through a defined threshold level. the control registers are then defined as below. after the first write command the bit will be reset to 0. cvout1=cvout2=1001, lo0 switch=lo1 switch=1, ycout1=ycout2=111, zcd switch=aout3 mute=1, aout1=aout2=111, group delay=10000, aout3=111, aout3 volume control coarse=aout3 volume control fine=111, aout3l/r switch=00, gd1 switch=gd2 switch=1, sync1 switch=sync2 switch=1. control register descriptions video inputs cvout1 data1 bits 4 to 7 these bits select the input signal that will be output on the cvout1 pin. cvout1 input or function selected 0000 tv 0001 cvin1 0010 cvin2 0011 y1 0100 y2 0101 y3 0110 y1+c1 0111 y2+c2 1000 y3+c3 1001 mute 1010 to 1111 not used cvout2 data1 bits 0 to 3 these bits select the input signal that will be output on the cvout2 pin. cvout2 input or function selected 0000 tv 0001 cvin1 0010 cvin2 0011 y1 0100 y2 0101 y3 0110 y1+c1 0111 y2+c2 1000 y3+c3 1001 mute 1010 to 111 not used
18 CXA2149Q ycout1 data2 bits 3 to 5 these bits select the input signals that will be output on the yout1/cout1 pins. ycout1/2 input or function selected 000 tv and mute 001 cvin1 and mute 010 cvin2 and mute 011 mute and mute 100 y1 and c1 101 y2 and c2 110 y3 and c3 111 mute and mute ycout2 data2 bits 0 to 2 these bits select the input signals that will be output on the yout2/cout2 pins. ycout2 input or function selected 000 tv and mute 001 cvin1 and mute 010 cvin2 and mute 011 mute and mute 100 y1 and c1 101 y2 and c2 110 y3 and c3 111 mute and mute
19 CXA2149Q audio inputs aout1 data3 bits 3 to 5 these bits select the input signal that will be output on the rout1 and lout1. aout1 bits input or function selected 000 mute 001 ltv and rtv 010 lv1 and rv1 011 lv2 and rv2 100 lv3 and rv3 101 lv4 and rv4 110 lv5 and rv5 111 mute aout2 data3 bits 0 to 2 these bits select the input signal that will be output on rout2 and lout2 aout2 bits input or function selected 000 mute 001 ltv and rtv 010 lv1 and rv1 011 lv2 and rv2 100 lv3 and rv3 101 lv4 and rv4 110 lv5 and rv5 111 mute aout3 data4 bits 0 to 2 these bits select the input signal that will be output on rout3 and lout3 aout3 bits input or function selected 000 mute 001 ltv and rtv 010 lv1 and rv1 011 lv2 and rv2 100 lv3 and rv3 101 lv4 and rv4 110 lv5 and rv5 111 mute
20 CXA2149Q group delay switches data1 bit 7 (gd1 switch) and bit 6 (gd2 switch) switch the respective group delay function on or off. gd2 switches on and off the group delay on the tv input and gd1 switches on and off the group delay on the cvin1 input. gd1 or gd2 bit group delay function 0 off 1 on group delay control data4 bits 3 to 7 used to control the variation in group delay. if no adjustment is required then set a value 10000. group delay bits change in the max. delay frequency 00000 C800 khz 11111 +800 khz aout3 volume control coarse data5 bits 5 to 7 selects the gain for the internal audio amplifiers in 8 db steps. coarse bits gain of aout3 channels 000 0 db 111 C56 db aout3 volume control fine data5 bits 2 to 4 selects the gain for the internal audio amplifiers in 1 db steps. fine bits gain of aout3 channels 000 0 db 111 C7 db aout3l/r switch data5 bits 0 and 1 controls which of channel 3s left or right channels is output to lout3 and rout3, respectively. aout3l/r bits output to lout3 and rout3 00 normal 01 left channel 10 right channel 11 inverted
21 CXA2149Q aout3 mute switch data3 bit 6 mutes the lout3 and rout3 channels at the electronic volume control output so that a click free audio channel change can take place. aout3 mute bit meaning 0 mute off 1 mute on the normal sequence for a click free channel change is as follows:- 1. mute the channel 3 outputs (aout3 mute=1) with zero cross detection on (zcd switch=1). 2. change the channel 3 audio source, aout3l/r control. 3. un-mute the channel 3 outputs still with zero cross detection on. lo0 or lo1 control data2 bit 7 (lo0 control) and bit 6 (lo1 control) used to control the switching of the open collector outputs. the output transistor emitters are connected to digital ground. each output is capable of sinking 1 ma. lo0 or lo1 bit collector output 0 low impedance 1 high impedance zero cross detection switch data3 bit 7 switches the zcd function on or off. when the zcd is on, a volume control change or mute instruction sent via the i 2 c bus will only be implemented when a minimal, ie., zero cross, signal amplitude is detected. zcd bit meaning 0 zcd off 1 zcd on sync id switches data6 bit 5 (sync1 switch) and bit 4 (sync2 switch) switches the respective sync id circuit to an input our output. sync1 switches between the tv input and yout1 output. sync2 switches between the cvin1 input and yout2 output. sync1 or sync2 bit input to sync id 0 yout1 and yout2 1 yv and cvin1 external logic inputs and output hardware mute the hardware mute (pin 17) provided will mute all audio outputs when the pin voltage exceeds 2.5 v. in this case the muting will be instantaneous. scart modes three mode inputs (pins 18, 19 and 20) are used to allow the format identification of up to three scart ports. see the description for mode status. lo0 and lo1 logic outputs lo0 and lo1 are open collector output i 2 c controllable logic switch for any external switching functions an application may require. see the description for lo0 and lo1 control.
22 CXA2149Q application diagram r e x t t v o u t r g d 4 r g d 3 l o 0 r g d 2 r g d 1 l o 1 c v o u t 1 t r a p 1 y o u t 1 v v c c 2 c o u t 1 s c l s d a a d r m u t e m o d e 1 m o d e 2 c 2 n c c 3 v g n d 2 c o u t 2 t r a p 2 y o u t 2 d v c c c v o u t 2 d g n d l o u t 2 r o u t 2 l o u t 1 r o u t 1 r v 1 r v 2 r v 3 r v 4 r v 5 r t v a g n d l v 1 l v 2 l v 3 l v 4 l v 5 l t v r o u t 3 l o u t 3 a b i a s a v c c m o d e 3 c 1 t r a p 3 y 3 v b i a s y 2 v g n d 1 y 1 v v c c 1 c v i n 2 t c 2 c v i n 1 t c 1 t v c x a 2 1 4 9 q 9 v 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 0 . 1 0 . 1 1 0 p 0 . 1 0 . 1 0 . 1 0 . 1 0 . 1 0 . 1 0 . 1 0 . 1 1 0 0 . 1 0 . 1 1 0 1 0 1 0 0 . 1 6 0 0 1 0 6 0 0 1 0 6 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 6 0 0 9 v 9 v 0 . 1 0 . 1 9 v 6 8 k 9 v 6 8 k 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 1 0 1 0 p 1 0 p 1 0 0 p 1 0 1 0 0 . 1 0 . 1 0 . 1 3 9 k ( 1 % ) 2 2 0 5 6 0 1 0 p 1 0 0 p 5 6 0 2 2 0 6 0 0 1 0 1 0 0 . 1 0 . 1 6 0 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 y 2 d r i v e y 1 d r i v e 1 8 0 1 8 0 9 v application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
23 CXA2149Q applications notes (see circuits diagram on next page). 1. care should be taken with polarity sensitive capacitors. the respective bias voltages for audio and video inputs and outputs are as follows. c1, c2, c3, cout1 and cout2 are biased at approximately 4.5 v. tv, cvin1, cvin2, y1, y2 and y3 are sync tip clamped at approximately 3.9 v. cvout1, cvout2, tvout have their sync tip output at approximately 3.5 v. yout1, yout2 have their sync tip output at approximately 3.3 v. abias and vbias are equal to approximately 4.5 v. 2. connect adr to v cc when wishing to set the slave address to 92h. 3. setting the mute pin to 2.5 v or more can mute the audio outputs. 4. trap1, trap2 and trap3 are set for a 3.58 mhz subcarrier. for a 4.43 mhz subcarrier typical values for the two traps would be 47 and 27 p, respectively. values may require adjustment dependent upon the application. each trap gives 6 dbs of attenuation at the desired frequency. 5. lo0 and lo1 connected to ground when not required. 6. connect all nc to ground in application.
24 CXA2149Q t y p i c a l a u d i o s y s t e m f r e q u e n c y r e s p o n s e l t v - l o u t 1 f r e q u e n c y [ h z ] a u d i o s y s t e m i n p u t / o u t p u t g a i n [ d b ] 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 4 2 0 2 4 6 8 1 0 v i d e o s y s t e m t y p i c a l f r e q u e n c y r e s p o n s e f r e q u e n c y [ m h z ] v i d e o s y s t e m i n p u t / o u t p u t g a i n [ d b ] 1 1 0 1 0 0 8 4 6 2 0 2 4 6 1 0 8 t y p i c a l a u d i o s y s t e m d i s t o r t i o n v s . i n p u t a m p l i t u d e i n p u t a m p l i t u d e [ v r m s ] t o t a l h a r m o n i c d i s t o r t i o n [ d b ] 1 . 5 2 2 . 5 0 . 5 1 3 0 4 0 3 0 2 0 1 0 5 0 6 0 7 0 8 0 9 0 1 1 0 1 0 0 f = 1 k h z 4 0 0 h z h p e , 8 0 k h z l p f t v - c v o u t 1 y 1 - c v o u t 2 ( m x ) example of representative characteristics
s o n y c o d e e i a j c o d e j e d e c c o d e 2 3 . 9 0 . 4 2 0 . 0 0 . 1 0 . 4 0 . 1 + 0 . 1 5 1 4 . 0 0 . 1 1 1 9 2 0 3 2 3 3 5 1 5 2 6 4 0 . 1 5 0 . 0 5 + 0 . 1 2 . 7 5 0 . 1 5 1 6 . 3 0 . 1 0 . 0 5 + 0 . 2 0 . 8 0 . 2 m 0 . 2 0 . 1 5 + 0 . 4 1 7 . 9 0 . 4 + 0 . 4 + 0 . 3 5 6 4 p i n q f p ( p l a s t i c ) q f p - 6 4 p - l 0 1 q f p 0 6 4 - p - 1 4 2 0 p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s e p o x y r e s i n s o l d e r / p a l l a d i u m 4 2 / c o p p e r a l l o y p a c k a g e s t r u c t u r e p l a t i n g 1 . 5 g 1 . 0 0 t o 1 0 package outline unit : mm CXA2149Q 25

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